Peripheral device

• Peripheral device, also known as peripheral, computer peripheral,input-output device, or input/output device, any of various devices (including sensors) used to enter information and instructions into a computer for storage or processing and to deliver the processed data to a human operator or, in some cases, a machine controlled by the computer. Such devices make up the peripheral equipment of modern digital computer systems.

• Peripheral  are commonly divided into three kinds: input devices, output devices, and storage devices (which partake of the characteristics of the first two). An input device converts incoming data and instructions into a pattern of electrical signals in binary code that are comprehensible to a digital computer. An output device reverses the process, translating the digitized signals into a form intelligible to the user. At one time punched-card and paper-tape readers were extensively used for inputting, but these have now been supplanted by more efficient devices.
• Input devices include typewriter-like keyboards; handheld devices such as the mouse trackball, joystick, trackpad, and special pen with pressure-sensitive pad; microphones, webcams, and digital cameras. They also include sensors that provide information about their environment—tempture , pressure and so forth—to a computer. Another direct-entry mechanism is the optical laser scanner (e.g., scanners used with point-of-sale terminals in retail stores) that can read bar-coded data or optical character fonts.

computer keyboard

• Output equipment includes video display terminal ink-jet and laser printers, loudspeakers, headphones, and devices such as flow valves that control machinery, often in response to computer processing of sensor input data. Some devices, such as video display terminals and USB hubs, may provide both input and output. Other examples are devices that enable the transmission and reception of data between computers—e.g., modems and network interfaces.

• Most auxiliary storage devices—as, for example, CD-ROM and DVD drives, flash memory drives, and external disk drives also double as input/output devices (see computer memory). Even devices such as smartphone, tablet computer and wearable devices like fitness trackers and smartwatch can be considered as peripherals, albeit ones that can function independently.

USB Flash-memory drive with USB

• Various standards for connecting peripherals to computers exist. For example, enhanced integrated drive electronic (EIDE) and serial advanced technology attachment (SATA) are common interfaces, or buses, for magnetic disk drives. A bus (also known as a port) can be either serial or parallel, depending on whether the data path carries one bit at a time (serial) or many at once (parallel). Serial connections, which use relatively few wires, are generally simpler and slower than parallel connections. Universal serial bus (USB) is a common serial bus. A common example of a parallel bus is the SATA bus.

Mode of Transfer:

• The binary information that is received from an external device is usually stored in the memory unit. The information that is transferred from the CPU to the external device is originated from the memory unit. CPU merely processes the information but the source and target is always the memory unit. Data transfer between CPU and the I/O devices may be done in different modes.
• Data transfer to and from the peripherals may be done in any of the three possible ways

1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA)

Direct Memory Access:

• Thus we can allow the peripherals directly communicate with each other using the memory buses, removing the intervention of the CPU. During DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit.

Types of DMA transfer using DMA controller:

Burst Transfer :

• DMA returns the bus after complete data transfer. 
  transfer.
  Steps involved are:

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1. Bus grant request time.
2. Transfer the entire block of data at transfer rate of device because the device is usually slow than the
   speed at which the data can be transferred to CPU.
3. Release the control of the bus back to CPU
   So, total time taken to transfer the N bytes
   = Bus grant request time + (N) * (memory transfer rate) + Bus release control time.

• Where, X µsec =data transfer time or preparation time (words/block) Y µsec =memory cycle time or cycle time or transfer time (words/block) % CPU idle (Blocked)=(Y/X+Y)*100 % CPU Busy=(X/X+Y)*100

Cyclic Stealing :

• An alternative method in which DMA controller transfers one word at a time after which it must return the control of the buses to the CPU. The CPU delays its operation only for one memory cycle to allow the direct memory I/O transfer to “steal” one memory cycle.
  Steps Involved are:

1. Buffer the byte into the buffer
2. Inform the CPU that the device has 1 byte to transfer (i.e. bus grant request)
3. Transfer the byte (at system bus speed)
4. Release the control of the bus back to CPU.

Interleaved mode: 

1. In this technique , the DMA controller takes over the system bus when the
   microprocessor is not using it.An alternate half cycle i.e. half cycle DMA + half cycle processor.

 Destination-initiated strobe for data transfer:

1.      In block diagram, we see that, the strobe initiated by destination, and as shown in timing diagram, the destination unit first activates the strobe pulse, informing the source to provide the data.
2. The source  unit responds by placing the requested binary information on the data bus.
3. The data must be valid  and remain in the bus long enough for the destination unit to accept it.
4.  Now, actually in computer, in the first case means in strobe initiated by source – the strobe may be a   memory-write control signal from the CPU to a memory unit.
5. The source, CPU, places the word on the data bus and informs the memory unit, which is the destination, that this is a write operation.

     Source initiated Handshaking:

     The source initiated transfer using handshaking lines is shown in figure  below:

     Destination initiated handshaking:

     The destination initiated transfer using handshaking lines is shown in figure  below:

• Thus, here we can say that, sequence of events in both cases would be identical.If we consider ready for data signal as the complement of data accept.Means, the only difference between source and destination initiated transfer is in their choice of initial state.

COA-Priority Interrupt

• But, in most cases there is a possibility that several sources will request service simultaneously.So, in this case, the interrupt system must also need to decide which device to service first.But, these simple interrupt system are not able for that, so, another system known as Priority interrupt system is provided.

Establishing Priority of Simultaneous Interrupt:

• The software method which gives priority to simultaneous interrupt is:
• Polling
• And the hardware method which gives priority to simultaneous interrupt is:
• Daisy-Chaining Priority
• Now, we will explore to each one of them one by one.

1. Polling:

• Polling is the software method of establishing priority of simultaneous interrupt.In this method, when  the processor detects an interrupt, it branches to an interrupt service routine whose job is to pull each I/O module to determine which module caused the interrupt.
• This is very simple method of establishing priority on simultaneous interrupt.But the disadvantage of polling is that it is very time consuming.

2. Daisy-Chaining Priority:

• The Daisy–Chaining method of establishing priority on interrupt sources uses the hardware i.e., it is the hardware means of establishing priority.
•     The figure shown below, this method of connection with three devices and the CPU.

    It works  as follows:

• In this way, it gave services to interrupt source according to their priority.And thus, we can say that, it       is the order of device in chain that determine the priority of interrupt sources.

Input/Output Processor

• An input-output processor (IOP) is a processor with direct memory access capability.
• Each IOP controls and manage the input-output tasks. The IOP is similar to CPU except that it handles only the details of I/O processing. The IOP can fetch and execute its own instructions.

Block Diagram Of I/O Processor

• Below is a block diagram of a computer along with various I/O Processors. The memory unit occupies the central position and can communicate with each processor.
• The CPU processes the data required for solving the computational tasks. The IOP provides a path for transfer of data between peripherals and memory. The CPU assigns the task of initiating the I/O program.
• The IOP operates independent from CPU and transfer data between peripherals and memory.

• The communication between the IOP and the devices is similar to the program control method of transfer. And the communication with the memory is similar to the direct memory access method.
• In large scale computers, each processor is independent of other processors and any processor can initiate the operation.
• The CPU can act as master and the IOP act as slave processor. The CPU assigns the task of initiating operations but it is the IOP, who executes the instructions, and not the CPU. CPU instructions provide operations to start an I/O transfer. The IOP asks for CPU through interrupt.

communication

• This transferring of data, either wirelessly or through wires, can be either one bit at a time or the entire data (depending on the size of the processor inside i.e., 8 bit, 16 bit etc.) at once. Based on this, we can have the following classification namely, Serial Communication and Parallel Communication.

Serial Communication

• Serial Communication implies transferring of data bit by bit, sequentially. Contrary to the parallel communication, serial communication needs only one line for the data transfer. 

Parallel Communication

• Parallel communication implies transferring of the bits in a parallel fashion at a time. This communication comes for rescue when speed rather than space is the main objective. The transfer of data is at high speed owing to the fact that no bus buffer is present.